1. Field of the Invention
The present invention relates generally to a phase interpolator and receiver, and more particularly, to a phase interpolator and receiver capable of ensuring operations to adjust clock phases into data phases.
2. Description of Related Art
FIG. 11 is a block diagram showing a high-speed input/output (I/O) device. A transmitter 4 converts input parallel data 1 into serial data 2. In this specification, the serial data is differential pair signals from CML (current mode logic). The converted serial data 2 is transmitted to a receiver 5. The receiver 5 receives the serial data 2 and converts it into parallel data 3. The serialization of parallel data into serial data and the deserialization of serial data into parallel data are carried out in synchronization with clock signals. The aerial data 2 from the transmitter 4 is asynchronous with the clock signals of the receiver 4. To correctly read the serial data 2 in the receiver 5, the serial data 2 must be synchronized with the clock signals. To achieve this, the phases of the clock signals must be synchronized with those of the serial data 2. To provide a function of adjusting the phases of clock signals to those of serial data, a phase interpolator (abbreviated as PI) and a data road circuit are employed.
FIG. 12 is a timing chart showing serial data 2′ supplied to a data read circuit and four-phase clock signals provided from a phase interpolator to the data read circuit. Among the four-phase clock signals, the signals Reclock_InIP 91 (positive=0) and Reclock_InIN 93 (negative=0) hit waveform centers of the serial data 2′, to correctly read the serial data 2′. If these clock signals hit the serial data 2′ shift, the serial data 2′ will incorrectly be read causing malfunctions in a receiver.
The signals Reclock_InIP 91 and Reclock_InIN 93 form a pair. Shifted from these signals by 90 degrees are signals Reclock_InQP and Reclock_InQN that form another pair.
FIG. 13 is a timing chart showing the clock signals Reclock_InIP 91 and Reclock_InIN 93 that have an improper duty ratio deviating from a proper duty ratio of 50:50 due to, for example, noise. The clock signal Reclock_InIP 91 hits a waveform center of the serial data 2′. The clock signal Reclock_InIN 93, however, hits a data transient position of the serial data 2′ due to the duty ratio deviation. This will cause a data read error.
FIG. 14 is a schematic view showing an output circuit of a phase interpolator according to a related art. A mixer 52 provides signals 61. These signals are slewed by an integrator 62, and the slewed signals are sent to an output buffer 63. The output buffer 63 amplifies the signals and provides output signals 65. The output signals 65 are sent to a data read circuit (not shown) and to a duty cycle correction circuit (DCC) 64 to correct duty ratios. The DCC 64 feeds duty correction signals back to the signals 61. The DCC 64 is capable of correcting the duty ratios of the signals 61.
The phase interpolator according to the related art, however, causes fluctuations in the voltage of the signals 61 due to parasitic capacitance and coupling capacitance that are affected by the operation of peripheral circuits.
FIG. 15 is a diagram showing signals 61′ that are affected by voltage fluctuations. The signals 61′ involve varying positive and negative voltage levels that move oppositely due to the CML (current mode logic), causing a small swing zone of reduced amplitude. The small swing zone is insufficiently amplified by the output buffer 63, and therefore, will not be recognized as a clock pulse by a data read circuit. In addition, the voltage variations deteriorate duty ratios, making the data read circuit unable to correctly read data.